View MAX1864_91423.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2030; Rev 0; 4/01
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
General Description
The MAX1864/MAX1865 power-supply controllers are designed to address cost-conscious applications such as cable modem Consumer Premise Equipment (CPE), xDSL CPE, and set-top boxes. Operating off a low-cost, unregulated DC supply (such as a wall adapter output), the MAX1864 generates three positive outputs, and the MAX1865 generates four positive outputs and one negative output to provide a cost-effective system power supply. The MAX1864 includes a current-mode synchronous step-down controller and two positive regulator gain blocks. The MAX1865 has one additional positive gain block and one negative regulator gain block. The main synchronous step-down controller generates a high-current output that is preset to 3.3V or adjustable from 1.236V to 0.8 V IN with an external resistivedivider. The 100kHz/200kHz operating frequency allows the use of low-cost aluminum-electrolytic capacitors and low-cost power magnetics. Additionally, the MAX1864/MAX1865 step-down controllers sense the voltage across the low-side MOSFET's on-resistance to efficiently provide the current-limit signal, eliminating the need for costly current-sense resistors. The MAX1864/MAX1865 generate additional supply rails at low cost. The positive regulator gain blocks use an external PNP pass transistor to generate low-voltage rails directly from the main step-down converter (such as 2.5V or 1.8V from the main 3.3V output) or higher voltages using coupled windings from the step-down converter (such as 5V, 12V, or 15V). The MAX1865's negative gain block uses an external NPN pass transistor in conjunction with a coupled winding to generate -5V, -12V, or -15V. All output voltages are externally adjustable, providing maximum flexibility. Additionally, the MAX1864/ MAX1865 feature soft-start for the step-down converter and all the positive linear regulators, and have a powergood output that monitors all of the output voltages. o 4.5V to 28V Input Voltage Range o Master DC-DC Step-Down Converter Preset 3.3V or Adjustable (1.236V to 0.8 VIN) Output Voltage Fixed-Frequency (100kHz/200kHz) PWM Controller No Current-Sense Resistor Adjustable Current Limit 95% Efficient o Two (MAX1864)/Four (MAX1865) Analog Gain Blocks Positive Analog Blocks Drive Low-Cost PNP Pass Transistors to Build Positive Linear Regulators Negative Analog Block (MAX1865) Drives a Low-Cost NPN Pass Transistor to Build a Negative Linear Regulator o Power-Good Indicator o Soft-Start Ramp for All Positive Regulators
Features
MAX1864/MAX1865
Ordering Information
PART MAX1864TEEE MAX1864UEEE MAX1865TEEP MAX1865UEEP TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 QSOP 16 QSOP 20 QSOP 20 QSOP fOSC (kHz) 200 100 200 100
Pin Configurations
TOP VIEW
POK 1 16 IN 15 VL 14 BST
Applications
xDSL, Cable, and ISDN Modems Set-Top Boxes Wireless Local Loop
COMP 2 OUT 3 FB 4 B2 5 FB2 6 B3 7 FB3 8
MAX1864
13 DH 12 LX 11 DL 10 GND 9 ILIM
16 QSOP
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
ABSOLUTE MAXIMUM RATINGS
IN, B2, B3, B4 to GND............................................-0.3V to +30V B5 to OUT...............................................................-20V to +0.3V VL, POK, FB, FB2, FB3, FB4, FB5 to GND ...............-0.3V to +6V LX to BST..................................................................-6V to +0.3V BST to GND ............................................................-0.3V to +36V DH to LX ....................................................-0.3V to (VBST + 0.3V) DL, OUT, COMP, ILIM to GND......................-0.3V to (VL + 0.3V) VL Output Current ...............................................................50mA VL Short Circuit to GND...................................................100ms Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)...........666mW 20-Pin QSOP (derate 9.1mW/C above +70C)...........727mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER GENERAL Operating Input Voltage Range (Note 1) Quiescent Supply Current VL REGULATOR Output Voltage Power-Supply Rejection Undervoltage Lockout Trip Level Minimum Bypass Capacitance DC-DC CONTROLLER Output Voltage (Preset Mode) Typical Output Voltage Range (Adjustable Mode) (Note 2) FB Set Voltage (Adjustable Mode) FB Dual ModeTM Threshold FB Input Leakage Current FB to COMP Transconductance Current-Sense Amplifier Voltage Gain Current-Limit Threshold (Internal Mode) Current-Limit Threshold (External Mode) IFB gm ALIM VVALLEY VVALLEY VFB = 1.5V FB = COMP, ICOMP = 5A VIN - VLX = 250mV VILIM = 5.0V VILIM = 2.5V 70 4.46 190 440 VOUT VOUT VSET FB = COMP FB = GND 3.272 1.236 1.221 50 1.236 100 0.01 100 4.9 250 530 3.314 3.355 0.8 x VIN 1.252 150 100 140 5.44 310 620 V V V mV nA S V/V mV mV VL PSRR VUVLO CBYP(MIN) 6V < VIN < 28V, 0.1mA < ILOAD < 20mA VIN = 6V to 28V VL rising, 3% hysteresis (typ) 10m < ESR < 500m 3.2 3.5 1 4.75 5.00 5.25 3 3.8 V % V F VIN VFB = 0, VOUT = 4V, VFB2 = VFB3 = VFB4 = 1.5V, VFB5 = -0.1V MAX1864 MAX1865 4.5 1.0 1.4 28 2 mA 3 V SYMBOL CONDITIONS MIN TYP MAX UNITS
IIN
Dual Mode is a trademark of Maxim Integrated Products, Inc. 2 _______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Switching Frequency Maximum Duty Cycle Soft-Start Period Soft-Start Steps DH Output Low Voltage DH Output High Voltage DL Output Low Voltage DL Output High Voltage DH, DL On-Resistance Output Drive Current LX, BST Leakage Current POSITIVE ANALOG GAIN BLOCKS FB2, FB3, FB4 Regulation Voltage FB2, FB3, FB4 to B_ Transconductance Feedback Input Leakage Current Driver Sink Current NEGATIVE ANALOG GAIN BLOCK FB5 Regulation Voltage FB5 to B5 Transconductance Feedback Input Leakage Current Driver Source Current POWER GOOD (POK) OUT Trip Level (Preset Mode) FB Trip Level (Adjustable Mode) FB2, FB3, FB4 Trip Level FB5 Trip Level POK Output Low Level POK Output High Leakage THERMAL PROTECTION (Note 3) Thermal Shutdown Thermal Shutdown Hysteresis Rising temperature 160 15 C C FB = GND, falling edge, 1% hysteresis (typ) Falling edge, 1% hysteresis (typ) Falling edge, 1% hysteresis (typ) Rising edge, 35mV hysteresis (typ) ISINK = 1mA VPOK = 5V 2.88 1.070 1.070 368 3 1.114 1.114 500 3.12 1.159 1.159 632 0.4 1 V V V mV V A VFB5 IFB5 IB5 VB5 = VOUT - 2V, VOUT = 3.5V, IB5 = 1mA (source) VB5 = 0, IB5 = 0.5mA to 5mA (source) VFB5 = -100mV VFB5 = 200mV, VB5 = VOUT - 2.0V, VOUT = 3.5V 10 -20 -5 -13 0.01 25 +10 -20 100 mV mV nA mA VFB_ IFB_ IB_ VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 1mA (sink) VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 0.5mA to 5mA (sink) VFB2 = VFB3 = VFB4 = 1.5V VFB2 = VFB3 = VFB4 = 1.188V VB2 = VB3 = VB4 = 2.5V VB2 = VB3 = VB4 = 4.0V 10 1.226 1.240 -1 0.01 23 26 1.257 -1.75 100 V % nA mA Sourcing or sinking, VDH or VDL = VL/2 VBST = VLX = VIN = 28V, VFB = 1.5V ISINK = 10mA, measured from DH to LX ISOURCE = 10mA, measured from BST to DH ISINK = 10mA, measured from DL to GND ISOURCE = 10mA, measured from DL to GND VL - 0.1 3 0.5 0.03 20 10 0.1 0.1 SYMBOL fOSC DMAX tSOFT MAX186_T MAX186_U CONDITIONS MIN 160 80 77 TYP 200 100 82 1024 VREF/64 0.1 MAX 240 120 90 UNITS kHz % 1/fOSC V V V V V A A
MAX1864/MAX1865
_______________________________________________________________________________________
3
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER GENERAL Operating Input Voltage Range (Note 1) Quiescent Supply Current VL REGULATOR Output Voltage Power-Supply Rejection Undervoltage Lockout Trip Level DC-DC CONTROLLER Output Voltage (Preset Mode) Feedback Set Voltage (Adjustable Mode) Current-Sense Amplifier Voltage Gain Current-Limit Threshold (Internal Mode) Current-Limit Threshold (External Mode) Switching Frequency Maximum Duty Cycle POSITIVE ANALOG GAIN BLOCKS FB2, FB3, FB4 Regulation Voltage FB2, FB3, FB4 to B_ Transconductance NEGATIVE ANALOG GAIN BLOCK FB5 Regulation Voltage FB5 to B5 Transconductance VFB5 VB5 = VOUT - 2V, VOUT = 3.5V, IB5 = 1mA (source) VB5 = 0, IB5 = 0.5mA to 5mA (source) -25 +10 -30 mV mV VFB_ VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 1mA (sink) VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 0.5mA to 5mA (sink) 1.215 1.265 -2.25 V % VOUT VSET ALIM VVALLEY VVALLEY fOSC DMAX FB = GND FB = COMP VIN - VLX = 250mV VILIM = 5V VILIM = 2.5V MAX186_T MAX186_U 3.247 1.211 4.12 150 400 160 80 74 3.380 1.261 5.68 350 660 240 120 90 V V V/V mV mV kHz % VL PSRR VUVLO 6V < VIN < 28V, 0.1mA < ILOAD <20mA VIN = 6V to 28V VL rising, 3% hysteresis (typ) 3 4.75 5.25 3 4 V % V VIN VFB = 0, VOUT = 4V, VFB2 = VFB3 = VFB4 = 1.5V, VFB5 = -0.1V MAX1864 MAX1865 4.5 28 2 mA 3 V SYMBOL CONDITIONS MIN MAX UNITS
IIN
4
_______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER POWER GOOD (POK) OUT Trip Level (Preset Mode) FB Trip Level (Adjustable Mode) FB2, FB3, FB4 Trip Level FB5 Trip Level FB = GND, falling edge, 1% hysteresis (typ) Falling edge, 1% hysteresis (typ) Falling edge, 1% hysteresis (typ) Rising edge, 35mV hysteresis (typ) 2.85 1.058 1.058 325 3.15 1.17 1.17 675 V V V mV SYMBOL CONDITIONS MIN MAX UNITS
MAX1864/MAX1865
Note 1: Note 2: Note 3: Note 4:
Connect VL to IN for operation with VIN < 5V. See Output Voltage Selection section. The internal 5V linear regulator (VL) powers the thermal shutdown block. Shorting VL to GND disables thermal shutdown. Specifications to -40C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT (PRESET MODE)
MAX1864/65 toc01
OUTPUT VOLTAGE vs. LOAD CURRENT (PRESET MODE)
MAX1864/65 toc02
EFFICIENCY vs. LOAD CURRENT (ADJUSTABLE MODE)
VIN = 6.5V 90 EFFICIENCY (%) VIN = 8V VIN = 12V 70 VIN = 18V VIN = 24V VOUT = 5.0V
MAX1864/65 toc03
100 VIN = 6.5V 90 EFFICIENCY (%)
3.33 3.32 OUTPUT VOLTAGE (V) 3.31 3.30 3.29 3.28
100
80 VIN = 8V 70 VIN = 12V VIN = 18V 60 VIN = 24V VOUT = 3.3V 50 0.01 0.1 1 10 LOAD CURRENT (A)
80
60
3.27 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A)
50 0.01 0.1 1 10 LOAD CURRENT (A)
_______________________________________________________________________________________
5
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
OUPUT VOLTAGE vs. LOAD CURRENT (ADJUSTABLE MODE)
MAX1864/65 toc04
INTERNAL 5V LINEAR REGULATOR vs. LOAD CURRENT
MAX1864/65 toc05
LOAD TRANSIENT (STEP-DOWN CONVERTER)
MAX1864/65 toc06
5.05
5.05
3.5V 3.3V 3.1V A
5.03 OUTPUT VOLTAGE (V)
5.03
4.99
VL (V)
5.01
5.01
4.99
1A B 0
4.97
4.97
4.95 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (mA)
4.95 0 5 10 15 20 25 30 LOAD CURRENT (mA) 1ms/div A. VOUT = 3.3V (PRESET), 200mV/div B. IOUT = 10mA TO 1A, 500mA/div VIN = 12V
SWITCHING WAVEFORMS (STEP-DOWN CONVERTER)
MAX1864/65 toc07
SOFT-START
MAX1864/65 toc08
POSITIVE LINEAR REGULATOR BASEDRIVE CURRENT vs. BASE-DRIVE VOLTAGE
35 30 25 20 15 10 5 0 B2, B3 AND B4 (MAX1865) ONLY 0 2 4 6 8 10 VFB_ = 0.96VREF VFB_ = 1.0V
MAX1864/65 toc09
40 A BASE-DRIVE SINK CURRENT (mA)
3.35V 3.30V 1.5A 1A 0.5A 10V 0 2s/div A. VOUT = 3.3V (PRESET), IOUT = 1A, 50mV/div B. INDUCTOR CURRENT, 500mA/div C. VLX, 10V/div VIN = 12V C B A
5V 0 4V 2V 0 1A C 0 1ms/div A. VL, 5V/div B. VOUT = 3.3V (PRESET), 2V/div C. INDUCTOR CURRENT, 1A/div VIN = 0 TO 12V B
BASE VOLTAGE (V)
6
_______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
POSITIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (QLDO = 2N3905)
MAX18664/65 toc10 MAX1864/65 toc11
MAX1864/MAX1865
POSITIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (QLDO = 2N3905)
2.50 2.50
POSITIVE LINEAR REGULATOR POWER-SUPPLY REJECTION RATIO (QLDO = 2N3905)
70 60 PSRR (dB) 50 40 30
MAX1864/65 toc12
80
2.48 OUTPUT VOLTAGE (V) VSUP(POS) = 5.0V 2.46 VSUP(POS) = 3.3V 2.44
OUTPUT VOLTAGE (V)
2.48 IOUT2 = 1mA 2.46 IOUT2 = 100mA
2.44
20 10 IOUT2 = 50mA
2.42 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA)
2.42 2 3 4 5 6 7 8 SUPPLY VOLTAGE (V)
0 0.1 1 10 FREQUENCY (kHz) 100 1000
POSITIVE LINEAR REGULATOR LOAD TRANSIENT (QLDO = 2W3905)
100mA
MAX1864/65 toc13
MAX1864/65 toc14
A OUTPUT VOLTAGE (V) 0
2.48
2.46
OUTPUT VOLTAGE (V)
VSUP(POS) = 5.0V
2.48
IOUT2 = 1mA
VSUP(POS) = 3.3V
2.46
IOUT2 = 100mA
2.467V B 2.457V
2.44
2.44
2.42 10s/div A. IOUTZ = 1mA TO 100mA, 50mA/div B. VOUTZ = 2.5V, 5mV/div CLDO(POS) = 10F CERAMIC, VSUP(POS) = 3.3V CIRCUIT OF FIGURE 1 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA)
2.42 2 4 6 8 10 12 SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX1864/65 toc15
2.50
POSITIVE LINEAR REGUALTOR OUTPUT VOLTAGE vs. LOAD CURRENT (QLDO = TIP30)
2.50
POSITIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (QLDO = TIP30)
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
MAX1864/65 toc16
60 PSRR (dB) 50 40 30 20 10 0 0.1 1 10 FREQUENCY (kHz) 100 IOUT2 = 150mA
0
A
BASE-DRIVE SOURCE CURRENT (mA)
70
250mA
40 35 30 25 20 15 10 5 0
VFB5 = 250mV
VFB5 = 50mV
2.473V B 2.453V 1000
VOUT = 5.0V VOUT = 3.3V B5 (MAX1865) ONLY 0 2 4 6 8 10
10s A. IOUT2 = 10mA TO 250mA, 200mA/div B. VOUT2 = 2.5V, 10mV/div CLDO(POS) = 10F CERAMIC, VSUP(POS) = 3.3V CIRCUIT OF FIGURE 1
VOUT - VB5 (V)
NEGATIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (QLDO = TIP29)
MAX1864/65 toc19
NEGATIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (QLDO = TIP29)
MAX1864/65 toc20
-12.00 VSUP(NEG) = -15V VOUT3 = 5V OUTPUT VOLTAGE (V) -12.06
-12.00
-12.12
OUTPUT VOLTAGE (V)
-12.06
-12.12 ILDO(NEG) = 100mA -12.18 ILDO(NEG) = 1mA
-12.18
-12.24 0.01 0.1 100 10 LOAD CURRENT (mA) 1 1000
-12.24 -20 -18 -16 -14 -12 -10 SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
MAX1864/65 toc18
80
POSITIVE LINEAR REGULATOR POWER-SUPPLY REJECTION RATIO (QLDO = TIP30)
POSITIVE LINEAR REGULATOR LOAD TRANSIENT (QLDO = TIP30)
MAX1864/65 toc17
NEGATIVE LINEAR REGULATOR BASEDRIVE CURRENT vs. BASE-DRIVE VOLTAGE
45
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
Pin Description
PIN MAX1864 1 MAX1865 1 NAME FUNCTION Open-Drain Power-Good Output. POK is low when the output voltage is more than 10% below the regulation point. POK is high impedance when the output is in regulation. Connect a resistor between POK and VL for logic-level voltages. Compensation Pin. Connect a series RC to GND to compensate the control loop. Typical values are 47k and 8.2nF. Regulated Output Voltage High-Impedance Sense Input. Internally connected to a resistive-divider and negative gain block (MAX1865). Dual-Mode Switching-Regulator Feedback Input. Connect to GND for the preset 3.3V output. Connect to a resistive-divider from output to FB to GND to adjust the output voltage between 1.236V and 0.8 VIN. The feedback set point is 1.236V. Open-Drain Output PNP Transistor Driver (Regulator #2). Internally connected to the drain of a DMOS. B2 connects to the base of an external PNP pass transistor to form a positive linear regulator. Analog Gain-Block Feedback Input (Regulator #2). Connect to a resistive-divider between the positive linear regulator's output and GND to adjust the output voltage. The feedback set point is 1.24V. Open-Drain Output PNP Transistor Driver (Regulator #3). Internally connected to the drain of a DMOS. B3 connects to the base of an external PNP pass transistor to form a positive linear regulator. Analog Gain-Block Feedback Input (Regulator #3). Connect to a resistive-divider between the positive linear regulator's output and GND to adjust the output voltage. The feedback set point is 1.24V. Open-Drain Output PNP Transistor Driver (Regulator #4). Internally connected to the drain of a DMOS. B4 connects to the base of an external PNP pass transistor to form a positive linear regulator. Analog Gain-Block Feedback Input (Regulator #4). Connect to a resistive-divider between the positive linear regulator's output and GND to adjust the output voltage. The feedback set point is 1.24V. Open-Drain Output NPN Transistor Driver (Regulator #5). Internally connected to the drain of a P-channel MOSFET. B5 connects to the base of an external NPN pass transistor to form a negative linear regulator. Analog Gain-Block Feedback Input (Regulator #5). Connect to a resistive-divider between the negative linear regulator's output and a positive reference voltage, typically one of the positive linear regulator outputs, to adjust the output voltage. The feedback set point is at GND.
MAX1864/MAX1865
POK
2 3
2 3
COMP OUT
4
4
FB
5
5
B2
6
6
FB2
7
7
B3
8
8
FB3
--
9
B4
--
10
FB4
--
11
B5
--
12
FB5
_______________________________________________________________________________________
9
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
Pin Description (continued)
PIN MAX1864 MAX1865 NAME FUNCTION Dual-Mode Current-Limit Adjustment Input. Connect to VL for the default 250mV current-limit threshold. In adjustable mode, the current-limit threshold voltage is 1/5th the voltage present at ILIM. Connect to a resistive-divider between VL and GND to adjust VILIM between 1V and 2.5V. The logic threshold for switchover to the 250mV default value is approximately VL - 1V. Ground Low-Side Gate-Driver Output. DL swings between GND and VL. Inductor Connection. Used for current sense between IN and LX, and used for current limit between LX and GND. High-Side Gate-Driver Output. DH swings between LX and BST. Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in the standard application circuit (Figures 1 and 6). Internal 5V Linear-Regulator Output. Supplies the IC and powers the DL low-side gate driver and external boost diode and capacitor. Bypass with a 1F or greater ceramic capacitor to GND. Input Supply Voltage, 4.5V to 28V. Bypass to GND with a 1F or greater ceramic capacitor close to the IC.
9
13
ILIM
10 11 12 13 14
14 15 16 17 18
GND DL LX DH BST
15
19
VL
16
20
IN
Detailed Description
The MAX1864/MAX1865 power-supply controllers provide system power for cable and xDSL modems. The main step-down DC-DC controller operates in a current-mode pulse-width-modulation (PWM) control scheme to ease compensation requirements and provide excellent load- and line-transient response. The MAX1864 includes two analog gain blocks to regulate two additional positive auxiliary output voltages, and the MAX1865 includes four analog gain blocks to regulate three additional positive and one negative auxiliary output voltages. The positive regulator gain blocks can be used to generate low-voltage rails directly from the main step-down converter or higher voltages using coupled windings from the step-down converter. The negative gain block can be used in conjunction with a coupled winding to generate -5V, -12V, or -15V.
DC-DC Controller
The MAX1864/MAX1865 step-down converters use a pulse-width-modulated (PWM) current-mode control scheme (Figure 2). An internal transconductance amplifier establishes an integrated error voltage at the COMP pin. The heart of the current-mode PWM controller is an open-loop comparator that compares the
10
integrated voltage-feedback signal against the amplified current-sense signal plus the slope compensation ramp. At each rising edge of the internal clock, the high-side MOSFET turns-on until the PWM comparator trips or the maximum duty cycle is reached. During this on-time, current ramps up through the inductor, sourcing current to the output and storing energy in a magnetic field. The current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. Since the average inductor current is nearly the same as the peak inductor current (assuming that the inductor value is relatively high to minimize ripple current), the circuit acts as a switchmode transconductance amplifier. It pushes the output LC filter pole, normally found in a voltage-mode PWM, to a higher frequency. To preserve inner loop stability and eliminate inductor stair-casing, a slope-compensation ramp is summed into the main PWM comparator. During the second-half of the cycle, the high-side MOSFET turns off and the low-side N-channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. Therefore, the output capacitor stores charge when the inductor current exceeds the load current and discharges when the inductor current is lower, smoothing
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
D1 CENTRAL CMPSH-3 INPUT 9V TO 18V NL, NH: INTERNATIONAL RECTIFIER IRF7303 Q1: TIP30 Q2: 2N3905
CIN 470F IN C1 1F DH CBST 0.1F VL C2 1F RPOK 100k POK LX RDL 10 ILIM DL NL BST RDH 10 NH T1 1 COUT 470F VOUT = 3.3V 1A
MAX1864
OUT GND
FB
CBE2 2200pF RBE2 220 R1 10k R2 10k C3 10F Q1 VOUT2 = 2.5V 300mA C4 10F T1
RCOMP 47k COMP CCOMP 8.2nF
B2
FB2
CBE3 4700pF RBE3 220 R3 30k C6 10F
D2 NIHON EP05Q03L C5 470F
B3
Q2
FB3 R4 10k
C7 10F
VOUT3 = 5.0V 100mA
Figure 1. Standard MAX1864 Application Circuit
the voltage across the load. Under overload conditions, when the inductor current exceeds the selected current-limit (see Current Limit), the high-side MOSFET is not turned on at the rising edge of the clock and the low-side MOSFET remains on to let the inductor current ramp down. The MAX1864/MAX1865 operate in a forced-PWM mode, so even under light loads the controller maintains a constant switching frequency to minimize crossregulation errors in applications that use a transformer. The low-side gate-drive waveform is the complement of the high-side gate-drive waveform, which causes the inductor current to reverse under light loads.
Current-Sense Amplifier The MAX1864/MAX1865s' current-sense circuit amplifies (AV = 5) the current-sense voltage generated by the high-side MOSFET's on-resistance (R DS(ON) IINDUCTOR). This amplified current-sense signal and the internal slope compensation signal are summed together (VSUM) and fed into the PWM comparator's inverting input. The PWM comparator turns-off the highside MOSFET when VSUM exceeds the integrated feedback voltage (VCOMP). Place the high-side MOSFET no further than 5mm from the controller, and connect IN and LX to the MOSFET using Kelvin sense connections to guarantee current-sense accuracy and improve stability.
______________________________________________________________________________________
11
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
BIAS OK
MAX1864 MAX1865
ENABLE
VREF
COMP OUT
THERMAL SHDN FB1
1.114V
3.5V FB IN SOFTSTART VREF 1.236V FB_ 100mV CLK BST B_ DH SLOPE COMP
AV = 5
VL LDO 5V VL
LX
DL AV = 5 0.9VREF FB1 100k 0.9VREF 400k ILIM OUT
GND
B5*
250mV 0.9 VL POK
FB5*
ENABLE 500mV *MAX1865 ONLY
Figure 2. Functional Diagram 12 ______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
Current-Limit Circuit The current-limit circuit employs a unique "valley" current-limiting algorithm that uses the low-side MOSFET's on-resistance as a sensing element (Figure 3). If the voltage across the low-side MOSFET (RDS(ON) IINDUCTOR ) exceeds the current-limit threshold at the beginning of a new oscillator cycle, the MAX1864/ MAX1865 will not turn on the high-side MOSFET. The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the lowside MOSFET on-resistance, inductor value, input voltage, and output voltage. The reward for this uncertainty is robust, loss-less overcurrent limiting. In adjustable mode, the current-limit threshold voltage is 1/5th the voltage seen at ILIM (IVALLEY = 0.2 VILIM). Adjust the current-limit threshold by connecting a resistive-divider from VL to ILIM to GND. The current-limit threshold can be set from 106mV to 530mV, which corresponds to ILIM input voltages of 500mV to 2.5V. This adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see Design Procedure). The current-limit threshold defaults to 250mV when ILIM is connected to VL. The logic threshold for switchover to the 250mV default value is approximately VL - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors don't corrupt the current-sense signals seen by LX and GND. The IC must be mounted close to the low-side MOSFET with short (less than 5mm), direct traces making a Kelvin sense connection. Synchronous Rectifier Driver (DL) Synchronous rectification reduces conduction losses in the rectifier by replacing the normal Schottky catch diode with a low-resistance MOSFET switch. The MAX1864/MAX1865 also use the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal. The DL low-side drive waveform is always the complement of the DH high-side drive waveform (with controlled dead time to prevent cross-conduction or "shoot-through"). A dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully off. For the dead-time circuit to work properly, there must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate. Otherwise, the sense circuitry in the MAX1864/ MAX1865 will interpret the MOSFET gate as "off" when gate charge actually remains. Use very short, wide
MAX1864/MAX1865
-IPEAK
ILOAD INDUCTOR CURRENT
IVALLEY
IPEAK = IVALLEY +
[
(VIN - VOUT) VOUT VINfOSC L
( )]
TIME
Figure 3. "Valley" Current-Limit Threshold Point
traces (50mil to 100mil wide if the MOSFET is 1 inch from the device). The dead time at the other edge (DH turning off) is determined by a fixed internal delay. High-Side Gate-Drive Supply (BST) Gate-drive voltage for the high-side N-channel switch is generated by a flying-capacitor boost circuit (Figure 1). The capacitor between BST and LX is alternately charged from the VL supply and placed parallel to the high-side MOSFET's gate-source terminals. On startup, the synchronous rectifier (low-side MOSFET) forces LX to ground and charges the boost capacitor to 5V. On the second half-cycle, the switchmode power supply turns on the high-side MOSFET by closing an internal switch between BST and DH. This provides the necessary gate-to-source voltage to turn on the high-side switch, an action that boosts the 5V gate-drive signal above the battery voltage.
Internal 5V Linear Regulator (VL)
All MAX1864/MAX1865 functions, except the currentsense amplifier, are internally powered from the onchip, low-dropout 5V regulator. The maximum regulator input voltage (VIN) is 28V. Bypass the regulator's output (VL) with at least a 1F ceramic capacitor to GND. The VIN-to-VL dropout voltage is typically 200mV, so when VIN is less than 5.2V, VL is typically VIN - 200mV. The internal linear regulator can source up to 20mA to supply the IC, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. When driving particularly large FETs, little or no regulator current may be available for external loads. For example, when switched at 200kHz, a large FET with 40nC total gate charge requires 40nC x 200kHz, or 8mA.
13
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
Undervoltage Lockout
If VL drops below 3.5V, the MAX1864/MAX1865 assume that the supply voltage is too low to make valid decisions, so the undervoltage lockout (UVLO) circuitry inhibits switching, forces POK low, and forces the DL and DH gate drivers low. After VL rises above 3.5V, internal digital soft-start is initiated (see Soft-Start).
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX1864/MAX1865. When the junction temperature exceeds TJ = +160C, a thermal sensor shuts down the device, forcing DL and DH low, allowing the IC to cool. The thermal sensor turns the part on again after the junction temperature cools by 10C, resulting in a pulsed output during continuous thermal-overload conditions. If the VL output is short circuited, thermaloverload protection is disabled. During a thermal event, the main step-down converter and the linear regulators are turned off, POK goes low, and soft-start is reset.
Startup Sequence
Externally, the MAX1864/MAX1865 starts switching when VL rises above the 3.5V undervoltage lockout threshold. However, the controller is not enabled unless all four of the following conditions are met: 1) VL exceeds the 3.5V undervoltage lockout threshold, 2) the internal reference exceeds 90% of its nominal value (VREF > 1.114V), 3) the internal bias circuitry powers up, and 4) the thermal limit is not exceeded. Once the MAX1864/MAX1865 assert the internal enable signal, the step-down controller starts switching and enables soft-start.
Design Procedure
DC-DC Step-Down Converter
Output Voltage Selection The step-down controller's feedback input features dual-mode operation. Connect the output to OUT and connect FB to GND for the preset 3.3V output voltage. Alternatively, the MAX1864/MAX1865 output voltage may be adjusted by connecting a voltage-divider from the output to FB to GND (Figure 4). Select R2 in the 5k to 50k range. Calculate R1 with the following equation: V R1 = R2 OUT - 1 VSET where V SET = 1.236V, and V OUT may range from 1.236V to approximately 0.8 x VIN (up to 20V). If VOUT > 5.5V, then connect OUT to GND (MAX1864) or to one of the positive linear regulators (MAX1865) with an output voltage between 2V and 5V. Inductor Value Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant LIR, which is the ratio of inductor peak-topeak AC current to DC load current. A higher LIR value allows smaller inductance but results in higher losses and higher output ripple. A good compromise between size and losses is a 30% ripple-current to load-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, selected LIR determine the inductor value as follows: L= VIN SW ILOAD(MAX)LIR VOUT (VIN - VOUT )
Soft-Start
Upon power-up, the MAX1864/MAX1865 begin a startup sequence. First, the reference powers up. Then, the main DC-DC step-down converter and positive linear regulators power up with soft-start enabled. Once the regulators reach 90% of their nominal value and softstart is complete, the active-high ready signal (POK) goes high (see Power-Good Output). Soft-start gradually ramps up to the reference voltage in order to control the rate of rise of the output voltages and reduce input surge currents during startup. The soft-start period is 1024 clock cycles (1024/fOSC), and the internal soft-start DAC ramps up the voltage in 64 steps. The output reaches regulation when soft-start is completed, regardless of output capacitance and load.
Power-Good Output
The power-good output (POK) is an open-drain output. The MOSFET turns on and pulls POK low when any output is less than 90% of its nominal regulation voltage or during soft-start. Once all of the outputs exceed 90% of their nominal regulation voltages and soft-start is completed, POK goes high impedance. To obtain a logic voltage output, connect a pullup resistor from POK to VL. A 100k resistor works well for most applications. If unused, leave POK grounded or unconnected.
14
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
D1 INPUT 4.5V TO 28V
IN C1
MAX1864 MAX1865
CIN BST DH CBST NH L COUT OUTPUT 1.25V TO 5V*
VL C2 ILIM RPOK POK RCOMP COMP CCOMP
LX NL
DL
OUT GND FB
R1
R2
* FOR OUTPUT VOLTAGES > 5V, SEE "OUTPUT VOLTAGE SELECTION."
Figure 4. Adjustable Output Voltage
where fSW is 200kHz for MAX186_T and 100kHz for MAX186_U. The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but at some point resistive losses due to extra turns of wire will exceed the benefit gained from lower AC current levels. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, though powdered iron is inexpensive and can work well at 200kHz. The chosen inductor's saturation rating must exceed the peak inductor current: LIR IPEAK = ILOAD(MAX) + I 2 LOAD(MAX) Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current at the minimum tolerance level of the current-limit circuit. The
valley of the inductor current occurs at I LOAD(MAX) minus half of the ripple current: VVALLEY(LOW) RDS(ON) LIR > ILOAD(MAX) - I 2 LOAD(MAX)
where R DS(ON) is the on-resistance of the low-side MOSFET (NL). For the MAX1864/MAX1865, the minimum current-limit threshold is 190mV (for the typical 250mV default setting). Use the worst-case maximum value for RDS(ON) from the MOSFET NL data sheet, and add some margin for the rise in RDS(ON) over temperature. A good general rule is to allow 0.5% additional resistance for each C of the MOSFET junction temperature rise. Connect ILIM to VL for the default 250mV (typ) currentlimit threshold. For an adjustable threshold, connect a resistive-divider from VL to ILIM to GND. The 500mV to 2.5V external adjustment range corresponds to a 106mV to 530mV current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a 10A divider current to prevent a significant increase in the current-limit tolerance.
______________________________________________________________________________________
15
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
MOSFET Selection The MAX1864/MAX1865s' step-down controller drives two external logic-level N-channel MOSFETs as the circuit switch elements. The key selection parameters are: * On-resistance (RDS(ON)) * Maximum drain-to-source voltage (VDS(MAX)) * Minimum threshold voltage (VTH(MIN)) * Total gate charge (Qg) * Reverse transfer capacitance (CRSS) The high-side N-channel MOSFET must be a logic-level type with guaranteed on-resistance specifications at VGS 4.5V. Select the high-side MOSFET's RDS(ON) so IPEAK x RDS(ON) 225mV for the current-sense range. For maximum efficiency, choose a high-side MOSFET (NH) that has conduction losses equal to the switching losses at the optimum input voltage. Check to ensure that the conduction losses at minimum input voltage don't exceed the package thermal limits or violate the overall thermal budget. Check to ensure that the conduction losses plus switching losses at the maximum input voltage don't exceed package ratings or violate the overall thermal budget. The low-side MOSFET (NL) provides the current-limit signal, so choose a MOSFET with an RDS(ON) large enough to provide adequate circuit protection (see Setting the Current-Limit): RDS(ON) = VVALLEY IVALLEY to ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case dissipation for the high-side MOSFET (PNH) occurs at both extremes of input voltage, and the worst-case dissipation for the low-side MOSFET (PNL) occurs at maximum input voltage. Duty Cycle : D = VOUT VIN
V C PNH(SWITCHING) = VINILOAD OSC IN RSS IGATE PNH(CONDUCTION) = ILOAD2 RDS(ON)NHD PNH( TOTAL) = PNH(SWITCHING) + PNH(CONDUCTION) PNL = ILOAD2 RDS(ON)NL (1 - D) where IGATE is the DH driver peak output current capability (1A typ), and 20ns is the DH driver inherent rise/fall-time. To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the highside switch drain to the low-side switch source, or add resistors (47 max) in series with DL and DH to increase the switches' turn-on and turn-off times (Figure 5). The minimum load current should exceed the high-side MOSFET's maximum leakage current over temperature if fault conditions are expected. Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation: VOUT ( VIN - VOUT ) VIN
Use the worst-case maximum value for RDS(ON) from the MOSFET NL data sheet, and add some margin for the rise in RDS(ON) over temperature. A good general rule is to allow 0.5% additional resistance for each C of the MOSFET junction temperature rise. Ensure that the MAX1864/MAX1865 DL gate drivers can drive NL; in other words, check that the dv/dt caused by NH turning on does not pull up the NL gate due to drain-to-gate capacitance, causing cross-conduction problems. MOSFET package power dissipation often becomes a dominant design factor. I2R power losses are the greatest heat contributor for both high-side and low-side MOSFETs. I2R losses are distributed between NH and NL according to duty factor as shown in the equations below. Generally, switching losses affect only the highside MOSFET since the low-side MOSFET is a zero-voltage switched device when used in the buck topology. Gate-charge losses are dissipated by the driver and do not heat the MOSFET. Calculate the temperature rise according to package thermal-resistance specifications
16
IRMS = ILOAD
For most applications, nontantalum capacitors (ceramic, aluminum, polymer, or OS-CON) are preferred due to their robustness with high inrush currents typical of systems with low-impedance battery inputs. Additionally, two (or more) smaller value low-ESR capacitors can be connected in parallel for lower cost. Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit long-term reliability.
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
MAX1864 MAX1865
BST RGATE (OPTIONAL) NH CBST RGATE (OPTIONAL) NL L
DH LX TO VL DH GND
With low-cost aluminum electrolytic capacitors, the ESR-induced ripple can be larger than that caused by the current into and out of the capacitor. Consequently, high-quality low-ESR aluminum-electrolytic, tantalum, polymer, or ceramic filter capacitors are required to minimize output ripple. Best results at reasonable cost are typically achieved with an aluminum-electrolytic capacitor in the 470F range, in parallel with a 0.1F ceramic capacitor. Since the MAX1864/MAX1865 use a current-mode control scheme, the output capacitor forms a pole that affects circuit stability (see Compensation Design). Furthermore, the output capacitor's ESR also forms a zero. The MAX1864/MAX1865s' response to a load transient depends on the selected output capacitor. After a load transient, the output instantly changes by ESR ILOAD. Before the controller can respond, the output will sag further, depending on the inductor and output capacitor values. After a short period of time (see Typical Operating Characteristics), the controller responds by regulating the output voltage back to its nominal state. For applications that have strict transient requirements, low-ESR high-capacitance electrolytic capacitors are recommended to minimize the transient voltage swing. Do not exceed the capacitor's voltage or ripple-current ratings.
MAX1864/MAX1865
Figure 5. Reducing the Switching EMI
Output Capacitor The key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (ESR), and voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. The output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor's ESR caused by the current into and out of the capacitor: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) The output voltage ripple as a consequence of the ESR and output capacitance is: VRIPPLE(ESR) = Ip-pESR Ip-p VRIPPLE(C) = 2COUT SW V -V V Ip-p = IN OUT OUT SW L VIN where IP-P is the peak-to-peak inductor current (see Inductor Selection). These equations are suitable for initial capacitor selection, but final values should be set by testing a prototype or evaluation circuit. As a general rule, a smaller ripple current results in less output ripple. Since the inductor ripple current is a factor of the inductor value and input voltage, the output voltage ripple decreases with larger inductance but increases with lower input voltages.
Compensation Design
The MAX1864/MAX1865 controllers use an internal transconductance error amplifier whose output compensates the control loop. Connect a series resistor and capacitor between COMP and GND to form a polezero pair. The external inductor, high-side MOSFET, output capacitor, compensation resistor, and compensation capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost. Additionally, the compensation resistor and capacitor are selected to optimize control-loop stability. The component values shown in the standard application circuits (Figures 1 and 6) yield stable operation over a broad range of input-to-output voltages. The controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the MAX1864/MAX1865 use the voltage across the highside MOSFET's RDS(ON) to sense the inductor current. Using the current-sense amplifier's output signal and the amplified feedback voltage, the control loop determines the peak inductor current by:
17
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
IPEAK = VOUT VREF A VEA VOUT(NOMINAL)RDS(ON)A VCS where the error amplifier's transconductance (gm) is 100S (see Electrical Characteristics). 4) Finally, select the compensation capacitor: CCOMP 1 2RCOMP POLE(OUT)
where AVCS is the current-sense amplifier's gain (4.9 typ), AVEA is the DC gain of the error amplifier (2000 typ), and VOUT(NOMINAL) is the output voltage set by the feedback resistive-divider (internal or external). Since the output voltage is a function of the load current and load resistance, the total DC loop gain (AV(DC)) is approximately: I VREFRLOADA VEA A V(DC) PEAK ILOAD VOUT(NOMINAL)RDS(ON)A VCS 400 x VREFRLOAD VOUT(NOMINAL)RDS(ON)
Boost-Supply Diode A signal diode, such as the 1N4148, works well in most applications. If the input voltage goes below 6V, use a small 20mA Schottky diode for slightly improved efficiency and dropout characteristics. Do not use large power diodes, such as the 1N5817 or 1N4001, since high junction capacitance can charge up VL to excessive voltages.
Linear Regulator Controllers
Positive Output Voltage Selection The MAX1864/MAX1865s' positive linear regulator output voltages are set by connecting a voltage-divider from the output to FB_ to GND (Figure 6). Select R4 in the 5k to 50k range. Calculate R3 with the following equation: V R3 = R4 OUT - 1 VFB where VFB = 1.24V, and VOUT may range from 1.24V to 30V. Negative Output Voltage Selection (MAX1865) The MAX1865's negative output voltage is set by connecting a voltage-divider from the output to FB5 to a positive voltage reference (Figure 6). Select R6 in the 5k to 50k range. Calculate R5 with the following equation: V R5 = R6 OUT VREF where VREF is the positive reference voltage used, and VOUT may be set between 0 and -20V. If the negative regulator is used, the OUT pin must be connected to a voltage supply between 2V and 5V that can source at least 25mA. Typically, the OUT pin is connected to the step-down converter's output. However, if the step-down converter's output voltage is set higher than 5V, OUT may be connected to one of the positive linear regulators with an output voltage between 2V and 5V.
The compensation capacitor (CCOMP) creates the dominant pole. Due to the current-mode control scheme, the output capacitor also creates a pole in the system that is a function of the load resistance. As the load resistance increases, the frequency of the output capacitor's pole decreases. However, the DC loop gain increases with larger load resistance, so the unity gain bandwidth remains fixed. Additionally, the compensation resistor and the output capacitor's ESR both generate zeros. Therefore, to achieve stable operation, use the following procedure to properly compensate the system: 1) First, select the desired crossover frequency. The crossover frequency must be less than both 1/5th the switching frequency and 1/3rd the zero frequency set by the output capacitor's ESR: c 1 6COUTRESR and SW 5
2) Next, determine the pole set by the output capacitor and the load resistor: ILOAD(MAX) 1 POLE(OUT) = = 2COUTRLOAD 2COUT VOUT 3) Determine the compensation resistor required to set the desired crossover frequency: RCOMP = 2000 x c gmA V(DC) POLE(OUT)
18
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
D1 CENTRAL CMPSH-3 INPUT 9V TO 18V
CIN 470F IN C1 1F DH CBST 0.1F VL C2 1F ILIM RPOK 100k TO LOGIC POK OUT GND DL LX RNL 10 NL BST RNH 10 NH
FAIRCHILD FDS6912A T1 1 VOUT1 3.3V AT 1A COUT 470F
FB
CBE2 2200pF RBE2 220 R1 10k
C3 10F
RCOMP 47k COMP CCOMP 8.2nF
B2
Q1 TIP30
VOUT2 2.5V AT 500mA C4 10F T1 1 D2 NIHON EP05Q03L C5 470F
FB2
MAX1865
R2 10k CBE3 4700pF RBE3 220 R3 30k C6 10F
B3
Q2 2N3905 VOUT3 5.0V AT 100mA D3 NIHON EP05Q03L CBE4 2200pF C9 10F C8 470F T1 2
FB3 C15 10nF B5 CBE5 2200pF R10 470 RBE5 220 FB5 B4 R9 470 FB4 C14 10nF R4 10k
C7 10F
C12 10F
Q4 TIP29
RBE4 220 R5 30k
RSNUB 300 CSNUB 100pF
Q3 TIP30 VOUT3 12V AT 100mA
C10 10F R6 10k
VOUT5 -12V AT 50mA
R8 120k C13 10F T1 C11 470F D4 NIHON EC10QS10 4 R7 50k
CONNECT TO VOUT3
Figure 6. Standard MAX1865 Application Circuit
______________________________________________________________________________________
19
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
Transistor Selection The pass transistors must meet specifications for current gain (hFE), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor's current gain limits the guaranteed maximum output current to: V ILOAD(MAX) = IDRV - BE hFE(MIN) RBE where IDRV is the minimum base-drive current, and RBE (220) is the pullup resistor connected between the transistor's base and emitter. Furthermore, the transistor's current gain increases the linear regulator's DC loop gain (see Stability Requirements), so excessive gain will destabilize the output. Therefore, transistors with current gain over 100 at the maximum output current, such as Darlington transistors, are not recommended. The transistor's input capacitance and input resistance also create a second pole, which could be low enough to destabilize the output when heavily loaded. The transistor's saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator will support. Alternatively, the package's power dissipation could limit the useable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor's package and mounting must exceed the actual power dissipation in the device. The power dissipated equals the maximum load current times the maximum input-to-output voltage differential: P = ILOAD(MAX) (VLDOIN - VOUT ) = ILOAD(MAX)VCE Stability Requirements The MAX1864/MAX1865 linear regulators use an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, pass transistor's specifications, the base-emitter resistor, and the output capacitor determine the loop stability. If the output capacitor and pass transistor are not properly selected, the linear regulator will be unstable. The transconductance amplifier regulates the output voltage by controlling the pass transistor's base current. Since the output voltage is a function of the load current and load resistance, the total DC loop gain (AV (LDO)) is approximately: 5.5 A V(LDO) VT IBIAShFE 1 + VREF ILOAD
where VT is 26mV, and IBIAS is the current through the base-to-emitter resistor (RBE). This bias resistor is typically 220, providing approximately 3.2mA of bias current. The output capacitor creates the dominant pole. However, the pass transistor's input capacitance creates a second pole in the system. Additionally, the output capacitor's ESR generates a zero, which may be used to cancel the second pole if necessary. Therefore, to achieve stable operation, use the following equations to verify that the linear regulator is properly compensated: 1) First, determine the dominant pole set by the linear regulator's output capacitor and the load resistor: POLE(CLDO) = ILOAD(MAX) 1 = 2CLDORLOAD 2CLDOVLDO
Unity Gain Crossover = A V(LDO) POLE(CLDO) 2) Next, determine the second pole set by the base-toemitter capacitance (including the transistor's input capacitance), the transistor's input resistance, and the base-to-emitter pullup resistor: POLE(CBE) = 2CBE RBE || RIN(NPN)
+ VThFE RI = BE LOAD 2CBERBEVThFE
(
1
)
3) A third pole is set by the linear regulator's feedback resistance and the capacitance between FB_ and GND, including 20pF stray capacitance: POLE(FB) = 1 2CFB(R1 || R2)
4) If the second and third poles occur well after unitygain crossover, the linear regulator will remain stable: POLE(CBE) > 2POLE(CLDO) A V(LDO) However, if the ESR zero occurs before unity-gain crossover, cancel the zero with POLE(FB) by changing circuit components such that:
20
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
POLE(FB) 1 2COUTRESR
MAX1864 MAX1865
B_ R1 VPOS FB_ R2 CLDO CBE RBE QPASS CBYP VSUP
Do not use output capacitors with more than 200m of ESR. Typically, more output capacitance provides the best solution, since this also reduces the output voltage drop immediately after a load transient. Linear Regulator Output Capacitors Connect at least a 1F capacitor between the linear regulator's output and ground, as close to the MAX1864/MAX1865 and external pass transistors as possible. Depending on the selected pass transistor, larger capacitor values may be required for stability (see Stability Requirements). Furthermore, the output capacitor's ESR affects stability, providing a zero that may be necessary to cancel the second pole. Use output capacitors with an ESR less than 200m to ensure stability and optimum transient response. Once the minimum capacitor value for stability is determined, verify that the linear regulator's output does not contain excessive noise. Although adequate for stability, small capacitor values may provide too much bandwidth, making the linear regulator sensitive to noise. Larger capacitor values reduce the bandwidth, thereby reducing the regulator's noise sensitivity. If noise on the ground reference causes the design to be marginally stable for the negative linear regulator, bypass the negative output back to its reference voltage (VREF, Figure 7). This technique reduces the differential noise on the output. Base-Drive Noise Reduction The high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. Capacitively coupled switching noise or inductively coupled EMI onto the base drive causes fluctuations in the base current, which appear as noise on the linear regulator's output. Keep the base-drive traces away from the step-down converter and as short as possible to minimize noise coupling. Resistors in series with the gate drivers (DH and DL) reduce the LX switching noise generated by the step-down converter (Figure 5). Additionally, a bypass capacitor may be placed across the base-to-emitter resistor (Figure 7). This bypass capacitor, in addition to the transistor's input capacitance, could bring in a second pole that will destabilize the linear regulator (see Stability Requirements). Therefore, the stability requirements determine the maximum base-to-emitter capacitance:
a) POSITIVE OUTPUT VOLTAGE
R4 VREF BF5 R3 VNEG B5 CBE RBE VSUP b) NEGATIVE OUTPUT VOLTAGE (MAX1865 ONLY) CBYP QPASS CNEG
MAX1865
Figure 7. Base-Drive Noise Reduction
CBE
RBEILOAD + VThFE - CIN(Q) 2 POLE(CBE) RBEVThFE 1
where CIN(Q) is the transistor's input capacitance, and fPOLE(CBE) is the second pole required for stability. Transformer Selection In systems where the step-down controller's output is not the highest voltage, a transformer may be used to provide additional postregulated, high-voltage outputs. The transformer generates unregulated, high-voltage supplies that power the positive and negative linear regulators. These unregulated supply voltages must be high enough to keep the pass transistors from saturating. For positive output voltages, connect the transformer as shown in figure 6 where the minimum turns ratio (N) is determined by: VLDO(POS) + VSAT + VDIODE NPOS -1 VOUT where VSAT is the pass transistor's saturation voltage under full load. For negative output voltages (MAX1865
______________________________________________________________________________________
21
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
only), connect the transformer as shown in Figure 6, where the minimum turns ratio is determined by: | VLDO(NEG) | + VSAT + VDIODE NNEG VOUT Since power transfer occurs when the low-side MOSFET is on (DL = high), the transformer cannot support heavy loads with high duty cycles. Snubber Design The MAX1864/MAX1865 use a current-mode control scheme that senses the current across the high-side MOSFET (NH). Immediately after the high-side MOSFET has turned on, the MAX1864/MAX1865 use a 60ns current-sense blanking period to minimize noise sensitivity. When the MOSFET turns on, however, the transformer's secondary inductance and the diode's parasitic capacitance form a resonant circuit that causes ringing. Reflected back through the transformer to the primary side, these oscillations across the high-side MOSFET may last longer than the blanking period. A series RC snubber circuit at the diode (Figure 6) increases the damping factor, allowing the ringing to settle quickly. Applications with multiple transformer windings require only one snubber circuit on the highest output voltage. Applications with low turn ratios (1:1), such as the MAX1864 typical application circuit (Figure 1), may not require a snubber curcuit. The diode's parasitic capacitance can be estimated using the diode's reverse voltage rating (VRRM), current capability (I O ), and recovery time (T RR ). A rough approximation is: I xt CDIODE = O RR VRRM For the EC10QS10 Nihon diode used in figure 6, the capacitance is roughly 15pF. The output snubber must only dampen the ringing, so the initial turn-on spike that occurs during the blanking period remains preset. A 100pF capacitor works well in most applications; larger capacitance values require more charge, thereby increasing the power dissipation. The snubber's time constant (tSNUB) must be smaller than the 100ns blanking time. A typical RC time constant of approximately 30ns was chosen for Figure 6: t 30ns RSNUB = SNUB = CSNUB CSNUB Minimum Load Requirements (Linear Regulators) Under no-load conditions, leakage currents from the pass transistors supply the output capacitor, even when the transistor is off. Generally, this is not a problem since the feedback resistors' current drains the excess charge. However, charge may build up on the output capacitor over temperature, making VLDO rise above its set point. Care must be taken to ensure that the feedback resistors' current exceeds the pass transistor's leakage current over the entire temperature range.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place the power components first, with ground terminals adjacent (NL source, CIN, COUT). If possible, make all these connections on the top layer with wide, copper-filled areas. Keep these high-current paths short, especially at ground terminals. 2) Mount the MAX1864/MAX1865 adjacent to the switching MOSFETs to keep IN-LX current-sense lines, LX-GND current-limit sense lines, and the driver lines (DL and DH) short and wide. The currentsense amplifier inputs are connected between IN and LX, so these pins must be connected as close as possible to the high-side MOSFET. The currentlimit comparator inputs are connected between LX and GND, but accuracy is not as important, so give priority to the high-side MOSFET connections. The IN, LX, and GND connections to the MOSFETs must be made using Kelvin sense connections to guarantee current-sense and current-limit accuracy. 3) Group the gate-drive components (BST diode and capacitor, IN bypass capacitor) together near the MAX1864/MAX1865. 4) All analog grounding must be done to a separate solid copper ground plane, which connects to the MAX1864/MAX1865 at the GND pin. This includes the VL bypass capacitor, feedback resistors, compensation components (R COMP , C COMP ), and adjustable current-limit threshold resistors connected to ILIM.
22
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
5) Ensure all feedback connections are short and direct. Place the feedback resistors as close to the MAX1864/MAX1865 as possible. 6) When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and low-side MOSFET or between the inductor and output filter capacitor. 7) Route high-speed switching nodes away from sensitive analog areas (B_, FB_, COMP, ILIM).
Pin Configurations (continued)
TOP VIEW
MAX1864/MAX1865
POK 1 COMP 2 OUT 3 FB 4 B2 5 FB2 6 B3 7 FB3 8 B4 9 FB4 10
20 IN 19 VL 18 BST 17 DH
MAX1865
16 LX 15 DL 14 GND 13 ILIM 12 FB5 11 B5
Regulating High Voltage
The linear regulator controllers can be configured to regulate high output voltages by adding a cascode transistor to buffer the base-drive output. For example, to generate an output voltage between 30V and 60V, add a 2N5550 high-voltage NPN transistor as shown in Figure 8a where VBIAS is a DC voltage between 3V and 20V that can source at least 1mA. RDROP protects the cascode transistor by decreasing the voltage across the transistor when the pass transistor saturates. Similarly, to regulate a negative output voltage between -20V and -120V, add a 2N5401 high-voltage PNP transistor as shown in Figure 8b.
20 QSOP
Chip Information
TRANSISTOR COUNT: 1617 PROCESS: BiCMOS
______________________________________________________________________________________
23
xDSL/Cable Modem Triple/Quintuple Output Power Supplies MAX1864/MAX1865
VBIAS CDROP RBE B_ QCASCODE QPASS RDROP VPOS FB_ R1 CPOS R2 a) POSITIVE OUTPUT VOLTAGE WITH CASCODED BASE DRIVE VSUP CBYP
MAX1864 MAX1865
R4 VREF FB5 R3 VNEG B5 QCASCODE RDROP QPASS RBE CDROP VSUP b) NEGATIVE OUTPUT VOLTAGE (MAX1865 ONLY) WITH CASCODED BASE DRIVE CBYP CNEG
MAX1865
Figure 8. High-Voltage Linear Regulation
Table 1. Component Suppliers
SUPPLIER INDUCTORS AND TRANSFORMERS Coilcraft Coiltronics Sumida USA Toko CAPACITORS AVX Kemet Panasonic Sanyo Taiyo Yuden DIODES Central Semiconductor International Nihon On Semiconductor Zetex 516-435-1110 310-322-3331 847-843-7500 602-303-5454 516-543-7100 516-435-1824 310-322-3332 847-843-2798 602-994-6430 516-864-7630 http://www.centralsemi.com http://www.irf.com http://www.niec.co.jp http://www.onsemi.com http://www.zetex.com 803-946-0690 408-986-0424 847-468-5624 619-661-6835 408-573-4150 803-626-3123 408-986-1442 847-468-5815 619-661-1055 408-573-4159 http://www.avxcorp.com http://www.kemet.com http://www.panasonic.com http://www.sanyo.com http://www.t-yuden.com 847-639-6400 561-241-7876 847-956-0666 847-297-0070 847-639-1469 561-241-9339 847-956-0702 847-699-1194 http://www.coilcraft.com http://www.coiltronics.com http://www.sumida.com http://www.toko.co.jp PHONE FAX INTERNET
24
______________________________________________________________________________________
xDSL/Cable Modem Triple/Quintuple Output Power Supplies
Package Information
QSOP.EPS
MAX1864/MAX1865
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX1864

	To Download MAX1864 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .